搜索资源列表
code-demo
- HM6264Driver_DS HM6264 RAM的读写驱动程序 S480_Manual_C S480的手动播放范例 （for SACMV26e.lib） SetIOBit SPCE061A 利用C语言进行软件端口位操作范例 ShowsinTable 简易正弦波发生器方案，同时提供全正数的正弦表 SleepTimerWakeup 定时中断唤醒CPU的范例 UARTDemo 使用UART中断方式进行通讯的范例 UARTDouble UART双机通讯范例，采用中断方
LPC1768-Xplorer
- LPC1768-Xplorer is a CORTEX-M3 based stamp board for NGX’s mbed-Xpresso Baseboard. The LPC1768 microcontroller has 512KB of internal flash and 64KB RAM. Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2
14SPI
- c8051f系列单片机的SPI 并行/串行通信源程序 Cygnal出的一种混合信号系统级单片机。片内含CIP－51的CPU内核，它的指令系统与MCS－51完全兼容。其中的C8051F020单片机含有64kB片内Flash程序存储器，4352B的RAM、8个I／O端口共64根I／O口线、一个12位A／D转换器和一个8位A／D转换器以及一个双12位D／A转换器、2个比较器、5个16位通用定时器、5个捕捉／比较模块的可编程计数／定时器阵列、看门狗定时器、VDD监视器和温度传感器等部分。C805
Using-the-Virtex-Block-SelectRAMP
- The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, o
IDT7005
- 双端口静态RAM的VHDL程序，具体芯片型号为IDT7005-DUAL-PORT STATIC RAM
HPI-Communication-Design
- 介绍了TMS320VC5402的HPI主机接口原理,以一个简单的通信程序作为例子,详细说明通过HPI 口实现5402芯片内部的16 kB 双端口RAM与AT 89 C51单片机的通信过程. -Introduces the principle of TMS320VC5402 HPI host interface, a simple communication program as an example, a detailed descr iption of the chip to achieve
Example-b4-1
- 1.定制一个双端口RAM，DualPortRAM 2.在顶层工程中实例化这个RAM 3.实现这个工程，在Quartus II仿真器中做门级仿真 在ModelSim中对这个工程进行RTL级仿真-1. Customize a dual-port RAM, DualPortRAM 2. In the top-level project instantiate RAM 3. To achieve this project, do gate-level simulator in Qua
Dual_ram_verilog_CODE
- 写了FIFO中要用到的双口RAM的模块,FIFO中的RAM只用于读数据,输出数据,用写时针采集信号,读时针那一端不用读时针来采样.-Written to use the FIFO dual port RAM module, FIFO in the RAM is only used to read data, output data, the clock signal acquisition with write and read without reading that end of the h
IDT7026
- 双口RAM驱动程序及测试，具体设计时可参考，采用sem实现-Dual-port RAM and test driver
QuartusII_IP_Core
- 以设计双端口RAM为例说明QuartusII中利用免费IP核的设计的详细教程-To design dual-port RAM as an example of the use of a detailed tutorial QuartusII free IP core design
dual_port_ram
- True dual port ram VHDL implementation
Synchronous-FIFO
- FIFO是英文FIRST-IN-FIRST-OUT的缩写，是一种先进先出的数据缓存器，它与普通存储器的区别是没有外部读写地址线，这样使用起来非常方便，但是缺点是只能顺序读写数据，其数据地址由内部读写指针自动加1完成 FIFO的主要功能是基于对双口RAM的读写控制来完成的，根据双口RAM的数据存储状况产生空满信号。双口RAM指的就是能同时对RAM进行读写操作的RAM存储器 -FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT,
dualporttst-1_1
- interfacing dual port ram in vhdl
Sunhaibo
- ＰＣＩ9054的读写，其中包括双口ＲＡＭ，以及寄存器的使用-PCI9054 read and write, which includes dual port RAM, as well as the use of registers
dual_ram
- 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
ram_2
- 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
fpga
- pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)